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1. general description the tda8950 is a high-ef?ciency class d audio power ampli?er. the typical output power is 2 150 w with a speaker load impedance of 4 w . the tda8950 is available in both hsop24 and dbs23p power packages. the ampli?er operates over a wide supply voltage range from 12.5 v to 40 v and features low quiescent current consumption. 2. features n pin compatible with tda8920b for both hsop24 and dbs23p packages n symmetrical operating supply voltage range from 12.5 v to 40 v n stereo full differential inputs, can be used as stereo single-ended (se) or mono bridge-tied load (btl) ampli?er n high output power in typical applications: u se 2 150 w, r l =4 w (v p = 37 v) u se 2 170 w, r l =4 w (v p = 39 v) u se 2 100 w, r l =6 w (v p = 37 v) u btl 1 300 w, r l =8 w (v p = 37 v) n low noise n smooth pop noise-free start-up and switch off n zero dead time switching n fixed frequency n internal or external clock n high ef?ciency n low quiescent current n advanced protection strategy: voltage protection and output current limiting n thermal foldback (tfb) n fixed gain of 30 db in se and 36 db in btl applications n fully short-circuit proof across load n bd modulation in btl con?guration 3. applications n dvd n mini and micro receiver n home theater in a box (htiab) system n high-power speaker system tda8950 2 150 w class-d power ampli?er rev. 02 11 june 2009 product data sheet
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 2 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 4. quick reference data [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] the circuit is dc adjusted at v p = 12.5 v to 32.5 v. [3] output power is measured indirectly; based on r dson measurement; see section 13.3 . 5. ordering information table 1. quick reference data symbol parameter conditions min typ max unit general, v p [1] = 30 v v p supply voltage operating mode [2] 12.5 35 40 v v p(ovp) overvoltage protection supply voltage standby, mute modes; v dd - v ss 85 - 90 v i q(tot) total quiescent current operating mode; no load; no ?lter; no rc-snubber network connected -5075ma stereo se con?guration p o output power t j =85 c; l lc =22 m h; c lc = 680 nf (see figure 10 ) [3] thd + n = 10 %; r l =4 w ; v p = 39 v 170 w thd + n = 0.5 %; r l = 4 w ; v p = 37 v - 100 - w thd + n = 10 %; r l = 4 w ; v p = 37 v - 150 - w thd + n = 10 %; r l = 6 w ; v p = 37 v - 100 - w mono btl con?guration p o output power t j =85 c; l lc =22 m h; c lc = 680 nf (see figure 10 ); r l =8 w ; thd + n = 10 %; v p = 37 v [3] - 300 - w table 2. ordering information type number package name description version tda8950j dbs23p plastic dil-bent-sil power package; 23 leads (straight lead length 3.2 mm) sot411-1 tda8950th hsop24 plastic, heatsink small outline package; 24 leads; low stand-off height sot566-3
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 3 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 6. block diagram pin numbers in brackets refer to type number tda8950j. fig 1. block diagram 001aah653 out1 v ssp1 v ddp2 driver high out2 boot2 tda8950th (tda8950j) boot1 driver low switch1 control and handshake pwm modulator manager oscillator temperature sensor current protection voltage protection stabi mode input stage mute 9 (3) 8 (2) in1m in1p 22 (15) 21 (14) 20 (13) 17 (11) 16 (10) 15 (9) vssp2 vssp1 driver high driver low switch2 control and handshake pwm modulator 11 (5) n.c. 7 (1) osc 2 (19) sgnd 6 (23) mode input stage mute 5 (22) 4 (21) in2m in2p 19 (-) 24 (17) vssd n.c. 1 (18) vssa 12 (6) n.c. 3 (20) vdda 10 (4) n.c. 23 (16) 13 (7) 18 (12) 14 (8) vddp2 prot stabi vddp1
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 4 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 7. pinning information 7.1 pinning fig 2. pin con?guration tda8950th fig 3. pin con?guration tda8950j tda8950th vssd vssa vddp2 sgnd boot2 vdda out2 in2m vssp2 in2p n.c. mode stabi osc vssp1 in1p out1 in1m boot1 n.c. vddp1 n.c. prot n.c. 001aah654 24 23 22 21 20 19 18 17 16 15 14 13 11 12 9 10 7 8 5 6 3 4 1 2 tda8950j osc in1p in1m n.c. n.c. n.c. prot vddp1 boot1 out1 vssp1 stabi vssp2 out2 boot2 vddp2 vssd vssa sgnd vdda in2m in2p mode 001aah655 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 5 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 7.2 pin description 8. functional description 8.1 general the tda8950 is a two-channel audio power ampli?er that uses class d technology. for each channel, the audio input signal is converted into a digital pwm signal using an analog input stage and a pwm modulator; see figure 1 . to drive the output power transistors, the digital pwm signal is fed to a control and handshake block and to high- and low-side driver circuits. this level-shifts the low-power digital pwm signal from a logic level to a high-power pwm signal switching between the main supply lines. a 2nd-order low-pass ?lter converts the pwm signal to an analog audio signal that can be used to drive a loudspeaker. table 3. pin description symbol pin description tda8950th tda8950j vssa 1 18 negative analog supply voltage sgnd 2 19 signal ground vdda 3 20 positive analog supply voltage in2m 4 21 channel 2 negative audio input in2p 5 22 channel 2 positive audio input mode 6 23 mode selection input: standby, mute or operating mode osc 7 1 oscillator frequency adjustment or tracking input in1p 8 2 channel 1 positive audio input in1m 9 3 channel 1 negative audio input n.c. 10 4 not connected n.c. 11 5 not connected n.c. 12 6 not connected prot 13 7 decoupling capacitor for protection (ocp) vddp1 14 8 channel 1 positive power supply voltage boot1 15 9 channel 1 bootstrap capacitor out1 16 10 channel 1 pwm output vssp1 17 11 channel 1 negative power supply voltage stabi 18 12 decoupling of internal stabilizer for logic supply n.c. 19 - not connected vssp2 20 13 channel 2 negative power supply voltage out2 21 14 channel 2 pwm output boot2 22 15 channel 2 bootstrap capacitor vddp2 23 16 channel 2 positive power supply voltage vssd 24 17 negative digital supply voltage
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 6 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er the tda8950 single-chip class d ampli?er contains high-power switches, drivers, timing and handshaking between the power switches, along with some control logic. to ensure maximum system robustness, an advanced protection strategy has been implemented to provide overvoltage, overtemperature and overcurrent protection. each of the two audio channels contains a pwm modulator, an analog feedback loop and a differential input stage. the tda8950 also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. the two independent ampli?er channels feature high output power, high ef?ciency, low distortion and low quiescent currents, and can be connected in the following con?gurations: ? stereo single-ended (se) ? mono bridge-tied load (btl) the ampli?er system can be switched to one of three operating modes using pin mode: ? standby mode: featuring very low quiescent current ? mute mode: the ampli?er is operational but the audio signal at the output is suppressed by disabling the voltage-to-current (vi converter) input stages ? operating mode: the ampli?er is fully operational, de-muted and can deliver an output signal a slowly rising voltage should be applied (e.g. via an rc network) to pin mode to ensure pop noise-free start-up. the bias-current setting of the (vi converter) input stages is related to the voltage on the mode pin. in mute mode, the bias-current setting of the vi converters is zero (vi converters are disabled). in operating mode, the bias current is at a maximum. the time constant required to apply the dc output offset voltage gradually between mute and operating mode levels can be generated using an rc network connected to pin mode. an example of a switching circuit for driving pin mode is illustrated in figure 4 . if the capacitor was omitted, the very short switching time constant could result in audible pop noises being generated at start-up (depending on the dc output offset voltage and loudspeaker used). fig 4. example of mode selection circuit 010aaa552 sgnd mode control mute/ operating 10 m f 5.6 k w + 5 v 470 w standby/ operating s2 s1 5.6 k w
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 7 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er to ensure the coupling capacitors at the inputs (c in in figure 10 ) are fully charged before the outputs start switching, a delay is inserted during the transition from mute to operating mode. an overview of the start-up timing is provided in figure 5 . for proper switch-off, the mode pin should be forced low at leaxt 100 ms before the supply lines (v dda and v ssa ) drop below 12.5 v. (1) first 1 4 pulse down. upper diagram: when switching from standby to mute, there is a delay of approximately 100 ms before the output starts switching. the audio signal will become available once v mode reaches the operating mode level (see t ab le 8 ), but not earlier than 150 ms after switching to mute. to start-up pop noise-free, it is recommended that the time constant applied to pin mode be at least 350 ms for the transition between mute and operating modes. lower diagram: when switching directly from standby to operating mode, there is a delay of 100 ms before the outputs start switching. the audio signal becomes available after a second delay of 50 ms. to start-up pop noise-free, it is recommended that the time-constant applied to pin mode be at least 500 ms for the transition between standby and operating modes. fig 5. timing on mode selection input pin mode 2.2 v < v mode < 3 v audio output operating standby mute 50 % duty cycle > 4.2 v 0 v (sgnd) time 001aah657 v mode 100 ms 50 ms modulated pwm > 350 ms 2.2 v < v mode < 3 v audio output operating standby mute 50 % duty cycle > 4.2 v 0 v (sgnd) time v mode 100 ms 50 ms modulated pwm > 350 ms (1) (1)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 8 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 8.2 pulse-width modulation frequency the ampli?er output signal is a pwm signal with a typical carrier frequency of between 250 khz and 450 khz. a 2nd-order lc demodulation ?lter on the output is used to convert the pwm signal into an analog audio signal. the carrier frequency is determined by an external resistor, r osc , connected between pins osc and vssa. the optimal carrier frequency setting is between 250 khz and 450 khz. the carrier frequency is set to 345 khz by connecting an external 30 k w resistor between pins osc and vssa. see t ab le 9 for more details. if two or more class d ampli?ers are used in the same audio application, it is recommended that an external clock circuit be used with all devices (see section 13.4 ). this will ensure that they operate at the same switching frequency, thus avoiding beat tones (if the switching frequencies are different, audible interference known as beat tones can be generated) 8.3 protection the following protection circuits are incorporated into the tda8950: ? thermal protection: C thermal foldback (tfb) C overtemperature protection (otp) ? overcurrent protection (ocp) ? window protection (wp) ? supply voltage protection: C undervoltage protection (uvp) C overvoltage protection (ovp) C unbalance protection (ubp) how the device reacts to a fault conditions depends on which protection circuit has been activated. 8.3.1 thermal protection the tda8950 employes an advanced thermal protection strategy. a tfb function gradually reduces the output power within a de?ned temperature range. if the temperature continues to rise, otp is activated to shut down the device completely. 8.3.1.1 thermal foldback (tfb) if the junction temperature (t j ) exceeds the thermal foldback activation threshold, the gain is gradually reduced. this reduces the output signal amplitude and the power dissipation, eventually stabilizing the temperature. tfb is speci?ed at the thermal foldback activation temperature t act(th_fold) where the closed-loop voltage gain is reduced by 6 db. the tfb range is: t act(th_fold) - 5 c < t act(th_fold) < t act(th_prot) the value of t act(th_fold) for the tda8950 is approximately 153 c; see t ab le 8 for more details.
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 9 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 8.3.1.2 overtemperature protection (otp) if tfb fails to stabilize the temperature and the junction temperature continues to rise, the ampli?er will shut down as soon as the temperature reaches the thermal protection activation threshold, t act(th_prot) . the ampli?er will resume switching approximately 100 ms after the temperature drops below t act(th_prot) . the thermal behavior is illustrated in figure 6 . 8.3.2 overcurrent protection (ocp) in order to guarantee the robustness of the tda8950, the maximum output current that can be delivered at the output stages is limited. ocp is built in for each output power switch. ocp is activated when the current in one of the power transistors exceeds the ocp threshold (i orm = 9.2 a) due, for example, to a short-circuit to a supply line or across the load. the tda8950 ampli?er distinguishes between low-ohmic short-circuit conditions and other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. the impedance threshold (z th ) depends on the supply voltage. how the ampli?er reacts to a short circuit depends on the short-circuit impedance: ? short-circuit impedance > z th : the ampli?er limits the maximum output current to i orm but the ampli?er does not shut down the pwm outputs. effectively, this results in a clipped output signal across the load (behavior very similar to voltage clipping). ? short-circuit impedance < z th : the ampli?er limits the maximum output current to i orm and at the same time discharges the capacitor on pin prot. when c prot is fully discharged, the ampli?er shuts down completely and an internal timer is started. the value of the protection capacitor (c prot ) connected to pin prot can be between 10 pf and 220 pf (typically 47 pf). while ocp is activated, an internal current source is enabled that will discharge c prot . (1) duty cycle of pwm output modulated according to the audio input signal. (2) duty cycle of pwm output reduced due to tfb. (3) ampli?er is switched off due to otp. fig 6. behavior of tfb and otp 001aah656 (t act(th_fold) - 5 c) t act(th_fold) t j ( c) t act(th_prot) gain (db) 30 db 24 db 0 db 12 3
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 10 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er when ocp is activated, the power transistors are turned off. they are turned on again during the next switching cycle. if the output current is still greater than the ocp threshold, they will be immediately switched off again. this switching will continue until c prot is fully discharged. the ampli?er will then be switched off completely and a restart sequence initiated. after a ?xed period of 100 ms, the ampli?er will attempt to switch on again, but will fail if the output current still exceeds the ocp threshold. the ampli?er will continue trying to switch on every 100 ms. the average power dissipation will be low in this situation because the duty cycle is low. switching the ampli?er on and off in this way will generate unwanted audio holes. this can be avoided by increasing the value of c prot (up to 220 pf) to delay ampli?er switch-off. c prot will also prevent the ampli?er switching off due to transient frequency-dependent impedance drops at the speakers. the ampli?er will switch on, and remain in operating mode, once the overcurrent condition has been removed. ocp ensures the tda8950 ampli?er is fully protected against short-circuit conditions while avoiding audio holes. [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] ovp can be triggered by supply pumping; see section 13.6 . 8.3.3 window protection (wp) window protection (wp) checks the conditions at the output terminals of the power stage and is activated: ? during the start-up sequence, when the tda8950 is switching from standby to mute. start-up will be interrupted if a short-circuit is detected between one of the output terminals and pin vddp1/vddp2 or vssp1/vssp2. the tda8950 will wait until the short-circuit to the supply lines has been removed before resuming start-up. the short circuit will not generate large currents because the short-circuit check is carried out before the power stages are enabled. ? when the ampli?er is shut down completely because the ocp circuit has detected a short circuit to one of the supply lines. wp will be activated when the ampli?er attempts to restart after 100 ms (see section 8.3.2 ). the ampli?er will not start-up again until the short circuit to the supply lines has been removed. table 4. current limiting behavior during low output impedance conditions at different values of c prot type v p [1] (v) v i (mv, p-p) f (hz) c prot (pf) pwm output stops short (z th =0 w ) short (z th = 0.5 w ) short (z th =1 w ) tda8950 29.5 500 20 10 yes yes ovp [2] 1000 10 yes yes no 20 15 yes yes ovp [2] 1000 15 yes no no 1000 220 no no no
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 11 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 8.3.4 supply voltage protection if the supply voltage drops below the minimum supply voltage threshold, v p(uvp) , the uvp circuit will be activated and the system will shut down. once the supply voltage rises above v p(uvp) again, the system will restart after a delay of 100 ms. if the supply voltage exceeds the maximum supply voltage threshold, v p(ovp) , the ovp circuit will be activated and the power stages will be shut down. when the supply voltage drops below v p(ovp) again, the system will restart after a delay of 100 ms. an additional unbalance protection (ubp) circuit compares the positive analog supply voltage (on pin vdda) with the negative analog supply voltage (on pin vssa) and is triggered if the voltage difference exceeds a factor of two (v dda > 2 | v ssa | or | v ssa | > 2 v dda ). when the supply voltage difference drops below the unbalance threshold, v p(ubp) , the system restarts after 100 ms. an overview of all protection circuits and their respective effects on the output signal is provided in t ab le 5 . [1] ampli?er gain depends on the junction temperature and heatsink size. [2] the ampli?er shuts down completely only if the short-circuit impedance is below the impedance threshold (z th ; see section 8.3.2 ). in all other cases, current limiting results in a clipped output signal. [3] fault condition detected during any standby-to-mute transition or during a restart after ocp has been activated (short-circuit to one of the supply lines). 8.4 differential audio inputs the audio inputs are fully differential ensuring a high common mode rejection ratio and maximum ?exibility in the application. ? stereo operation: to avoid acoustical phase differences, the inputs should be in antiphase and the speakers should be connected in antiphase. this con?guration: C minimizes power supply peak current C minimizes supply pumping effects, especially at low audio frequencies ? mono btl operation: the inputs must be connected in anti-parallel. the output of one channel is inverted and the speaker load is connected between the two outputs of the tda8950. in practice (because of the ocp threshold) the output power can be boosted to twice the output power that can be achieved with the single-ended con?guration. the input con?guration for a mono btl application is illustrated in figure 7 . table 5. overview of tda8950 protection circuits protection name complete shutdown restart directly restart after 100 ms pin prot detection tfb [1] nnnn otp y n y n ocp y [2] n [2] y [2] y wp n [3] ynn uvpynyn ovp y n y n ubpynyn
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 12 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 9. limiting values [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. 10. thermal characteristics fig 7. input con?guration for mono btl application v in in1p out1 power stage mbl466 out2 sgnd in1m in2p in2m table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v p [1] supply voltage standby, mute modes; v dd - v ss -90 v i orm repetitive peak output current maximum output current limiting 9.2 - a t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c t j junction temperature - 150 c v mode voltage on pin mode referenced to sgnd 0 6 v v osc voltage on pin osc 0 sgnd + 6 v v i input voltage referenced to sgnd; pin in1p; in1m; in2p and in2m - 5+5 v v prot voltage on pin prot referenced to voltage on pin vssd 0 12 v v esd electrostatic discharge voltage human body model (hbm) - 2000 +2000 v charged device model (cdm) - 500 +500 v i q(tot) total quiescent current operating mode; no load; no ?lter; no rc-snubber network connected -75 ma v pwm(p-p) peak-to-peak pwm voltage on pins out1 and out2 - 120 v table 7. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 40 k/w r th(j-c) thermal resistance from junction to case 1.1 k/w
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 13 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 11. static characteristics [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] the circuit is dc adjusted at v p = 12.5 v to 42.5 v. [3] unbalance protection activated when v dda > 2 | v ssa | or | v ssa | > 2 v dda . [4] with respect to sgnd (0 v). [5] the transition between standby and mute modes has hysteresis, while the slope of the transition between mute and operating modes is determined by the time-constant of the rc network on pin mode; see figure 8 . [6] dc output offset voltage is gradually applied to the output during the transition between mute and operating modes. the slop e caused by any dc output offset is determined by the time-constant of the rc network on pin mode. [7] at a junction temperature of approximately t act(th_fold) - 5 c, gain reduction commences and at a junction temperature of approximately t act(th_prot) , the ampli?er switches off. table 8. static characteristics v p = 35 v; f osc = 345 khz; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v p [1] supply voltage operating mode [2] 12.5 30 40 v v p(ovp) overvoltage protection supply voltage standby, mute modes; v dd - v ss 85 - 90 v v p(uvp) undervoltage protection supply voltage v dd - v ss 20 - 25 v v p(ubp) unbalance protection supply voltage [3] -33-% i q(tot) total quiescent current operating mode; no load; no ?lter; no rc-snubber network connected - 5075ma i stb standby current measured at 30 v - 480 650 m a mode select input; pin mode v mode voltage on pin mode referenced to sgnd [4] 0- 6v standby mode [4] [5] 0 - 0.8 v mute mode [4] [5] 2.2 - 3.0 v operating mode [4] [5] 4.2 - 6 v i i input current v i = 5.5 v - 110 150 m a audio inputs; pins in1m, in1p, in2p and in2m v i input voltage dc input [4] -0-v ampli?er outputs; pins out1 and out2 v o(offset) output offset voltage se; mute mode - - 25 mv se; operating mode [6] -- 150 mv btl; mute mode - - 30 mv btl; operating mode [6] -- 210 mv stabilizer output; pin stabi v o(stabi) output voltage on pin stabi mute and operating modes; with respect to vssd 9.3 9.8 10.3 v temperature protection t act(th_prot) thermal protection activation temperature - 154 - c t act(th_fold) thermal foldback activation temperature closed loop se voltage gain reduced with 6 db [7] - 153 - c
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 14 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 12. dynamic characteristics 12.1 switching characteristics [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] when using an external oscillator, the frequency f track (500 khz minimum, 900 khz maximum) will result in a pwm frequency f osc (250 khz minimum, 450 khz maximum) due to the internal clock divider; see section 8.2 . [3] when t r(i) > 100 ns, the output noise ?oor will increase. fig 8. behavior of mode selection pin mode standby mute on 5.5 coa021 v mode (v) 4.2 3.0 2.2 0.8 0 v o (v) v o(offset)(mute) v o(offset)(on) slope is directly related to the time-constant of the rc network on the mode pin table 9. dynamic characteristics v p [1] = 35 v; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit internal oscillator f osc(typ) typical oscillator frequency r osc = 30.0 k w 290 345 365 khz f osc oscillator frequency 250 - 450 khz external oscillator input or frequency tracking; pin osc v osc voltage on pin osc high-level sgnd + 4.5 sgnd + 5 sgnd + 6 v v trip trip voltage - sgnd + 2.5 - v f track tracking frequency [2] 500 - 900 khz z i input impedance 1 - - m w c i input capacitance - - 15 pf t r(i) input rise time from sgnd + 0 v sgnd + 5 v [3] - - 100 ns
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 15 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 12.2 stereo se con?guration characteristics [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] r sl is the series resistance of the low-pass lc ?lter inductor used in the application. [3] output power is measured indirectly; based on r dson measurement; see section 13.3 . [4] thd measured between 22 hz and 20 khz, using aes17 20 khz brick wall ?lter; max. limit is guaranteed but may not be 100 % tested. [5] v ripple = v ripple(max) = 2 v (p-p); measured independently between vddpn and sgnd and between vsspn and sgnd. [6] 22 hz to 20 khz, using aes17 20 khz brick wall ?lter. [7] 22 hz to 20 khz, using aes17 20 khz brick wall ?lter. table 10. dynamic characteristics v p [1] = 35 v; r l = 4 w ; f i = 1 khz; f osc = 345 khz; r sl [2] < 0.1 w ; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit p o output power t j =85 c; l lc =22 m h; c lc = 680 nf (see figure 10 ) [3] thd + n = 10 %; r l =4 w ; v p = 39 v 170 w thd + n = 0.5 %; r l = 4 w ; v p = 37 v - 100 - w thd + n = 10 %; r l = 4 w ; v p = 37 v - 150 - w thd + n = 10 %; r l = 6 w ; v p = 37 v - 100 - w thd total harmonic distortion p o = 1 w; f i = 1 khz [4] - 0.05 - % p o = 1 w; f i = 6 khz [4] - 0.05 - % g v(cl) closed-loop voltage gain 29 30 31 db svrr supply voltage ripple rejection between pins vddpn and sgnd operating mode; f i = 100 hz [5] -90-db operating mode; f i = 1 khz [5] -70-db mute mode; f i = 100 hz [5] -75-db standby mode; f i = 100 hz [5] - 120 - db between pins vsspn and sgnd operating mode; f i = 100 hz [5] -80-db operating mode; f i = 1 khz [5] -60-db mute mode; f i = 100 hz [5] -80-db standby mode; f i = 100 hz [5] - 115 - db z i input impedance between one of the input pins and sgnd 45 63 - k w v n(o) output noise voltage operating mode; r s =0 w [6] - 160 - m v mute mode [7] -85- m v a cs channel separation [8] -70-db |d g v | voltage gain difference - - 1 db a mute mute attenuation f i = 1 khz; v i = 2 v (rms) [9] -75-db cmrr common mode rejection ratio v i(cm) = 1 v (rms) - 75 - db h po output power ef?ciency se, r l = 4 w -88-% se, r l = 6 w -90-% btl, r l = 8 w -88-% r dson(hs) high-side drain-source on-state resistance [10] - 200 - m w r dson(ls) low-side drain-source on-state resistance [10] - 190 - m w
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 16 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er [8] p o = 1 w; f i = 1 khz. [9] v i = v i(max) = 1 v (rms); f i = 1 khz. [10] leads and bond wires included. 12.3 mono btl application characteristics [1] v p is the supply voltage on pins vddp1, vddp2 and vdda. [2] r sl is the series resistance of the low-pass lc ?lter inductor used in the application. [3] output power is measured indirectly; based on r dson measurement; see section 13.3 . [4] thd measured between 22 hz and 20 khz, using aes17 20 khz brick wall ?lter; max. limit is guaranteed but may not be 100 % tested. [5] v ripple = v ripple(max) = 2 v (p-p). [6] 22 hz to 20 khz, using an aes17 20 khz brick wall ?lter; low noise due to bd modulation. [7] 22 hz to 20 khz, using an aes17 20 khz brick wall ?lter. [8] v i = v i(max) = 1 v (rms); f i = 1 khz. table 11. dynamic characteristics v p [1] = 35 v; r l = 8 w ; f i = 1 khz; f osc = 345 khz; r sl [2] < 0.1 w ; t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit p o output power t j =85 c; l lc =22 m h; c lc = 680 nf (see figure 10 ) [3] thd + n = 10 %; r l = 8 w ; v p = 39 v - 340 - w thd + n = 0.5 %; r l = 8 w ; v p = 37 v - 200 - w thd + n = 10 %; r l = 8 w ; v p = 37 v - 300 - w thd total harmonic distortion p o = 1 w; f i = 1 khz [4] - 0.05 - % p o = 1 w; f i = 6 khz [4] - 0.05 - % g v(cl) closed-loop voltage gain - 36 - db svrr supply voltage ripple rejection between pin vddpn and sgnd operating mode; f i = 100 hz [5] -80-db operating mode; f i = 1 khz [5] -80-db mute mode; f i = 100 hz [5] -95-db standby mode; f i = 100 hz [5] - 120 - db between pin vsspn and sgnd operating mode; f i = 100 hz [5] -75-db operating mode; f i = 1 khz [5] -75-db mute mode; f i = 100 hz [5] -90-db standby mode; f i = 100 hz [5] - 130 - db z i input impedance measured between one of the input pins and sgnd 45 63 - k w v n(o) output noise voltage operating mode; r s =0 w [6] - 190 - m v mute mode [7] -45- m v a mute mute attenuation f i = 1 khz; v i = 2 v (rms) [8] -75-db cmrr common mode rejection ratio v i(cm) = 1 v (rms) - 75 - db
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 17 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 13. application information 13.1 mono btl application when using the power ampli?er in a mono btl application, the inputs of the two channels must be connected in parallel and the phase of one of the inputs must be inverted; see figure 7 . in principle, the loudspeaker can be connected between the outputs of the two single-ended demodulation ?lters. 13.2 pin mode to ensure a pop noise-free start-up, an rc time-constant must be applied to pin mode. the bias-current setting of the vi converter input is directly related to the voltage on pin mode. in turn the bias-current setting of the vi converters is directly related to the dc output offset voltage. a slow dv/dt on pin mode results in a slow dv/dt for the dc output offset voltage, ensuring a pop noise-free transition between mute and operating modes. a time-constant of 500 ms is suf?cient to guarantee pop noise-free start-up; see figure 4 , figure 5 and figure 8 for more information. 13.3 estimating the output power 13.3.1 single-ended (se) maximum output power: (1) maximum output current is internally limited to 9.2 a: (2) where: ? p o(0.5 %) : output power at the onset of clipping ? r l : load impedance ? r dson(hs) : high-side r dson of power stage output dmos (temperature dependent) ? r sl : series impedance of the ?lter coil ? v p : single-sided supply voltage or 0.5 (v dd + | v ss | ) ? t w(min) : minimum pulse width (typical 150 ns, temperature dependent) ? f osc : oscillator frequency remark: note that i o(peak) should be less than 9.2 a ( section 8.3.2 ). i o(peak) is the sum of the current through the load and the ripple current. the value of the ripple current is dependent on the coil inductance and the voltage drop across the coil. p o 0.5 % () r l r l r dson hs () r sl ++ ---------------------------------------------------- - v p 1t w min () 0.5 f osc C () 2 2r l ------------------------------------------------------------------------------------------------------------------------------- ---------- = i opeak () v p 1t w min () 0.5 f osc C () r l r dson hs () r sl ++ --------------------------------------------------------------------- =
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 18 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 13.3.2 bridge-tied load (btl) maximum output power: (3) maximum output current internally limited to 9.2 a: (4) where: ? p o(0.5 %) : output power at the onset of clipping ? r l : load impedance ? r dson(hs) : high-side r dson of power stage output dmos (temperature dependent) ? r dson(ls) : low-side r dsson of power stage output dmos (temperature dependent) ? r sl : series impedance of the ?lter coil ? v p : single-sided supply voltage or 0.5 (v dd + | v ss | ) ? t w(min) : minimum pulse width (typical 150 ns, temperature dependent) ? f osc : oscillator frequency remark: note that i o(peak) should be less than 9.2 a; see section 8.3.2 .i o(peak) is the sum of the current through the load and the ripple current. the value of the ripple current is dependent on the coil inductance and the voltage drop across the coil. 13.4 external clock to ensure duty cycle-independent operation, the external clock frequency is divided by two internally. the external clock frequency is therefore twice the internal clock frequency (typically 2 350 khz = 700 khz). if several class d ampli?ers are used in a single application, it is recommended that all the devices run at the same switching frequency. this can be achieved by connecting the osc pins together and feeding them from an external oscillator. when using an external oscillator, it is necessary to force pin osc to a dc level above sgnd. this disables the internal oscillator and causes the pwm to switch at half the external clock frequency. the internal oscillator requires an external resistor r osc , connected between pin osc and pin vssa. r osc must be removed when using an external oscillator. the noise generated by the internal oscillator is supply voltage dependent. an external low-noise oscillator is recommended for low-noise applications running at high supply voltages. p o 0.5 % () r l r l r dson hs () r dson ls () ++ ------------------------------------------------------------------- 2v p 1t wmin () 0.5 f osc C () 2 2r l ------------------------------------------------------------------------------------------------------------------------------- ---------------------------- = i opeak () 2v p 1t w min () 0.5 f osc C () r l r dson hs () r dson ls () + () 2r sl ++ ------------------------------------------------------------------------------------------ - =
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 19 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 13.5 heatsink requirements an external heatsink must be connected to the tda8950. equation 5 de?nes the relationship between maximum power dissipation before activation of tfb and total thermal resistance from junction to ambient. (5) power dissipation (p) is determined by the ef?ciency of the tda8950. ef?ciency measured as a function of output power is given in figure 20 . power dissipation can be derived as a function of output power as shown in figure 19 . (1) r th(j-a) = 5 k/w. (2) r th(j-a) = 10 k/w. (3) r th(j-a) = 15 k/w. (4) r th(j-a) = 20 k/w. (5) r th(j-a) = 35 k/w. fig 9. derating curves for power dissipation as a function of maximum ambient temperature r th ja C () t j t amb C p ----------------------- - = p (w) 30 20 10 0 t amb ( c) (1) (2) (3) (4) (5) 0 20 100 40 60 80 mbl469
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 20 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er in the following example, a heatsink calculation is made for an 8 w btl application with a 30 v supply: the audio signal has a crest factor of 10 (the ratio between peak power and average power (20 db)); this means that the average output power is 1 10 of the peak power. thus, the peak rms output power level is the 0.5 % thd level, i.e. 170 w. the average power is then 1 10 170w=17w. the dissipated power at an output power of 17 w is approximately 7 w. when the maximum expected ambient temperature is 50 c, the total r th(j-a) becomes r th(j-a) = r th(j-c) + r th(c-h) + r th(h-a) r th(j-c) (thermal resistance from junction to case) = 1.1 k/w r th(c-h) (thermal resistance from case to heatsink) = 0.5 k/w to 1 k/w (dependent on mounting) so the thermal resistance between heatsink and ambient temperature is: r th(h-a) (thermal resistance from heatsink to ambient) = 14 - (1.1 + 1) = 11.9 k/w the derating curves for power dissipation (for several r th(j-a) values) are illustrated in figure 9 . a maximum junction temperature t j = 150 c is taken into account. the maximum allowable power dissipation for a given heatsink size can be derived, or the required heatsink size can be determined, at a required power dissipation level; see figure 9 . 13.6 pumping effects in a typical stereo single-ended con?guration, the tda8950 is supplied by a symmetrical supply voltage (e.g. v dd = 30 v and v ss = - 30 v). when the ampli?er is used in an se con?guration, a pumping effect can occur. during one switching interval, energy is taken from one supply (e.g. v dd ), while a part of that energy is returned to the other supply line (e.g. v ss ) and vice versa. when the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source increases and the supply voltage is pumped to higher levels. the voltage increase caused by the pumping effect depends on: ? speaker impedance ? supply voltage ? audio signal frequency ? value of supply line decoupling capacitors ? source and sink currents of other channels pumping effects should be minimized to prevent the malfunctioning of the audio ampli?er and/or the voltage supply source. ampli?er malfunction due to the pumping effect can trigger uvp, ovp or ubp. 148 50 C () 7 ------------------------- 14 k/w =
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 21 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er the most effective way to avoid pumping effects is to connect the tda8950 in a mono full-bridge con?guration. in the case of stereo single-ended applications, it is advised to connect the inputs in anti-phase (see section 8.4 ). the power supply can also be adapted; for example, by increasing the values of the supply line decoupling capacitors. 13.7 application schematic notes on the application schematic: ? connect a solid ground plane around the switching ampli?er to avoid emissions ? place 100 nf capacitors as close as possible to the tda8950 power supply pins ? connect the heatsink to the ground plane or to vsspn using a 100 nf capacitor ? use a thermally conductive, electrically non-conductive, sil-pad between the tda8950 heat spreader and the external heatsink ? the heat spreader of the tda8950 is internally connected to vssd ? use differential inputs for the most effective system level audio performance with unbalanced signal sources. in case of hum due to ?oating inputs, connect the shielding or source ground to the ampli?er ground.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 22 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er (1) the value of c prot can be in the range 10 pf to 220 pf (see section 8.3.2 ) fig 10. typical application diagram 010aaaxxx c in in1p in1 + - + - in2 in1m sgnd 2 3 19 22 21 20 18 470 nf 470 nf c in c in in2p in2m 470 nf 470 nf c in 220 nf vdda vssa 17 7 v ssp vdda vssa prot 13 14 15 vssp vssp2 out2 boot2 16 vddp vddp2 vssd c vdda 220 nf c vssa 100 nf c vddp 15 nf c bo 100 nf c vssp 100 nf c vp vssp vssp vssp vddp vddp vddp + - + - 11 vssp1 8 vddp1 23 mode mode control 1 osc 6 4 n.c. 5 n.c. n.c. 100 nf c vddp 100 nf c vssp 100 nf c vp c prot (1) v ssa 12 stabi c stab 470 nf r osc 30 k w 10 9 out1 boot1 15 nf c bo l lc vssa r vdda 10 w r vssa 10 w c vp 22 m f c vddp 470 m f c vssp 470 m f gnd vddp vssp vdda vddp vssp vssa r sn 10 w r sn 10 w c sn 220 pf c sn 220 pf c sn 220 pf c lc c lc c sn 220 pf r zo 22 w c zo 100 nf r zo 22 w c zo 100 nf load l lc c lc 3 w to 6 w 15 m h 680 nf 4 w to 8 w 22 m h 470 nf single-ended output filter values tda8950j l lc sgnd mode control mute/ operating 10 m f 5.6 k w + 5 v 470 w standby/ operating 5.6 k w t2 hfe > 80 t1 hfe > 80 470 k w + 5 v 470 k w 10 k w 10 k w
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 23 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 13.8 curves measured in reference design v p = 35 v, f osc = 345 khz, 2 4 w se con?guration. (1) f i = 6 khz. (2) f i = 1 khz. (3) f i = 100 hz. fig 11. thd + n as a function of output power, se con?guration with 2 4 w load v p = 35 v, f osc = 345 khz, 2 6 w se con?guration. (1) f i = 6 khz. (2) f i = 1 khz. (3) f i = 100 hz. fig 12. thd + n as a function of output power, se con?guration with 2 6 w load 010aaa553 10 - 1 10 - 2 1 10 thd (%) 10 - 3 p o (w) 10 - 2 10 3 10 2 10 - 1 110 (1) (2) (3) 010aaa554 10 - 1 10 - 2 1 10 thd (%) 10 - 3 p o (w) 10 - 2 10 3 10 2 10 - 1 110 (2) (1) (3)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 24 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f osc = 345 khz, 1 8 w btl con?guration. (1) f i = 6 khz. (2) f i = 1 khz. (3) f i = 100 hz. fig 13. thd + n as a function of output power, btl con?guration with 1 8 w load v p = 35 v, f osc = 345 kh, 2 4 w se con?guration. (1) p o = 1 w. (2) p o = 10 w. fig 14. thd + n as a function of frequency, se con?guration with 2 4 w load 001aai423 10 - 1 10 - 2 1 10 thd (%) 10 - 3 p o (w) 10 - 2 10 3 10 2 10 - 1 110 (1) (2) (3) 001aai424 10 - 1 10 - 2 1 10 thd (%) 10 - 3 f i (hz) 10 10 5 10 4 10 2 10 3 (1) (2)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 25 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f osc = 345 khz, 2 6 w se con?guration. (1) p o = 1 w. (2) p o = 10 w. fig 15. thd + n as a function of frequency, se con?guration with 2 6 w load v p = 35 v, f osc = 345 khz, 1 8 w btl con?guration. (1) p o = 1 w. (2) p o = 10 w. fig 16. thd + n as a function of frequency, btl con?guration with 1 8 w load 001aai701 10 - 1 10 - 2 1 10 thd (%) 10 - 3 f i (hz) 10 10 5 10 4 10 2 10 3 (1) (2) 001aai702 10 - 1 10 - 2 1 10 thd (%) 10 - 3 f i (hz) 10 10 5 10 4 10 2 10 3 (1) (2)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 26 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f osc = 345 khz, 2 4 w se con?guration. 1 w and 10 w respectively. fig 17. channel separation as a function of frequency, se con?guration with 2 4 w load v p = 35 v, f osc = 345 khz, 2 6 w se con?guration. 1 w and 10 w respectively. fig 18. channel separation as a function of frequency, se con?guration with 2 6 w load 001aai703 f i (hz) 10 10 5 10 4 10 2 10 3 - 60 - 40 - 80 - 20 0 a cs (db) - 100 001aai704 f i (hz) 10 10 5 10 4 10 2 10 3 - 60 - 40 - 80 - 20 0 a cs (db) - 100
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 27 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f i = 1 khz; f osc = 345 khz. (1) 2 4 w se con?guration. (2) 2 6 w se con?guration. (3) 2 8 w se con?guration. fig 19. power dissipation as a function of output power per channel, se con?guration v p = 35 v, f i = 1 khz, f osc = 345 khz. (1) 2 8 w se con?guration. (2) 2 6 w se con?guration. (3) 2 4 w se con?guration. fig 20. ef?ciency as a function of output power per channel, se con?guration p o (w) 0 120 80 40 20 100 60 001aai705 20 10 30 40 p (w) 0 25 15 35 5 (1) (2) (3) p o (w) 0 120 80 40 20 100 60 001aai706 40 20 100 h (%) 0 60 80 (1) (2) (3)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 28 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er in?nite heat sink used. f i = 1 khz, f osc = 345 khz. (1) thd + n = 10 %, 4 w . (2) thd + n = 0.5 %, 4 w ; thd + n = 10 %, 6 w . (3) thd + n = 10 %, 8 w ; thd + n = 0.5 %, 6 w (4) thd + n = 0.5 %, 8 w . fig 21. output power as a function of supply voltage, se con?guration in?nite heat sink used. f i = 1 khz, f osc = 345 khz. (1) thd + n = 10 %, 8 w . (2) thd + n = 0.5 %, 8 w . (3) thd + n = 10 %, 16 w . (4) thd + n = 0.5 %, 16 w . fig 22. output power as a function of supply voltage, btl con?guration v p (v) 12.5 40 32.5 30 22.5 25 15 17.5 20 37.5 35 27.5 001aai707 60 20 100 120 140 160 200 40 80 180 p o (w) 0 (1) (2) (3) (4) v p (v) 12.5 40 32.5 30 22.5 25 15 17.5 20 37.5 35 27.5 001aai708 150 50 250 350 100 200 300 p o (w) 0 (1) (2) (3) (4)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 29 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f osc = 345 khz, v i = 100 mv, c i = 330 pf, l lc = 15 m h, c lc = 680 nf. (1) 1 8 w btl con?guration. (2) 2 4 w se con?guration. (3) 2 6 w se con?guration. (4) 2 8 w se con?guration. fig 23. closed-loop voltage gain as a function of frequency ripple on v dd , short on input pins. v p = 35 v, f osc = 345 khz, r l = 4 w , v ripple = 2 v (p-p). (1) mute mode. (2) operating mode. (3) standby mode. fig 24. svrr as a function of ripple frequency, ripple on v dd 001aai709 f i (hz) 10 10 5 10 4 10 2 10 3 30 35 25 40 45 g v(cl) (db) 20 (1) (2) (3) (4) 001aai710 f ripple (hz) 10 10 5 10 4 10 2 10 3 - 100 - 80 - 60 - 40 - 20 svrr (db) - 140 - 120 (3) (2) (1)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 30 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er ripple on v ss , short on input pins. v p = 35 v, f osc = 345 khz, r l = 4 w , v ripple = 2 v (p-p). (1) mute mode. (2) operating mode. (3) standby mode. fig 25. svrr as a function of ripple frequency, ripple on v ss v p = 35 v, f osc = 345 khz. (1) mode voltage down. (2) mode voltage up. fig 26. output voltage as a function of mode voltage 001aai711 f ripple (hz) 10 10 6 10 4 10 2 10 3 - 100 - 80 - 60 - 40 - 20 svrr (db) - 140 - 120 (3) (1) (2) v mode (v) 0 5 4 23 1 4.5 3.5 1.5 2.5 0.5 001aai712 10 - 4 10 - 5 10 - 3 10 - 2 10 - 1 10 1 v o (v) 10 - 6 (1) (2)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 31 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er v p = 35 v, f osc = 325 khz, v i = 2 v (rms). (1) 8 w . (2) 6 w . (3) 4 w . fig 27. mute attenuation as a function of frequency 001aai713 f i (hz) 10 10 5 10 4 10 2 10 3 - 70 - 80 - 60 - 50 a mute (db) - 90 (1) (2) (3)
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 32 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 14. package outline fig 28. package outline sot411-1 (dbs23p) unit a 2 references outline version european projection issue date iec jedec jeita mm 4.6 4.3 a 4 1.15 0.85 a 5 1.65 1.35 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot411-1 98-02-20 02-04-24 0 5 10 mm scale d l l 1 l 2 e 2 e c a 4 a 5 a 2 m l 3 e 1 q w m b p 1 d z e 2 e e 123 j dbs23p: plastic dil-bent-sil power package; 23 leads (straight lead length 3.2 mm) sot411-1 v m d x h e h non-concave view b : mounting base side b b e 1 b p cd (1) e (1) z (1) de d h ll 3 m 0.75 0.60 0.55 0.35 30.4 29.9 28.0 27.5 12 2.54 12.2 11.8 10.15 9.85 1.27 e 2 5.08 2.4 1.6 e h 6 e 1 14 13 l 1 10.7 9.9 l 2 6.2 5.8 e 2 1.43 0.78 2.1 1.8 1.85 1.65 4.3 3.6 2.8 q j 0.25 w 0.6 v 0.03 x 45 b
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 33 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er fig 29. package outline sot566-3 (hsop24) unit a 4 (1) references outline version european projection issue date 03-02-18 03-07-23 iec jedec jeita mm + 0.08 - 0.04 3.5 0.35 dimensions (mm are the original dimensions) notes 1. limits per individual lead. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot566-3 0 5 10 mm scale hsop24: plastic, heatsink small outline package; 24 leads; low stand-off height sot566-3 a max. detail x a 2 3.5 3.2 d 2 1.1 0.9 h e 14.5 13.9 l p 1.1 0.8 q 1.7 1.5 2.7 2.2 v 0.25 w 0.25 yz 8 0 q 0.07 x 0.03 d 1 13.0 12.6 e 1 6.2 5.8 e 2 2.9 2.5 b p c 0.32 0.23 e 1 d (2) 16.0 15.8 e (2) 11.1 10.9 0.53 0.40 a 3 a 4 a 2 (a 3 ) l p q a q d y x h e e c v m a x a b p w m z d 1 d 2 e 2 e 1 e 24 13 1 12 pin 1 index
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 34 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 35 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 15.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 30 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 12 and 13 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 30 . table 12. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 13. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 36 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 16. soldering of through-hole mount packages 16.1 introduction to soldering through-hole mount packages this text gives a very brief insight into wave, dip and manual soldering. wave soldering is the preferred method for mounting of through-hole mount ic packages on a printed-circuit board. 16.2 soldering by dipping or by solder wave driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.3 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 c and 400 c, contact may be up to 5 seconds. msl: moisture sensitivity level fig 30. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 37 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 16.4 package related soldering information [1] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] for pmfp packages hot bar soldering or manual soldering is suitable. 17. revision history table 14. suitability of through-hole mount ic packages for dipping and wave soldering package soldering method dipping wave cpga, hcpga - suitable dbs, dip, hdip, rdbs, sdip, sil suitable suitable [1] pmfp [2] - not suitable table 15. revision history document id release date data sheet status change notice supersedes tda8950_2 20090611 product data sheet tda8950_1 modi?cations ? parameter values revised throughout. ? revised figure 4 , figure 10 , figure 11 and figure 12 . tda8950_1 20080909 preliminary data sheet - -
tda8950_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 11 june 2009 38 of 39 nxp semiconductors tda8950 2 150 w class-d power ampli?er 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 18.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors tda8950 2 150 w class-d power ampli?er ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 11 june 2009 document identifier: tda8950_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 pulse-width modulation frequency . . . . . . . . . . 8 8.3 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.3.1 thermal protection . . . . . . . . . . . . . . . . . . . . . . 8 8.3.1.1 thermal foldback (tfb) . . . . . . . . . . . . . . . . . 8 8.3.1.2 overtemperature protection (otp) . . . . . . . . . 9 8.3.2 overcurrent protection (ocp) . . . . . . . . . . . . . 9 8.3.3 window protection (wp). . . . . . . . . . . . . . . . . 10 8.3.4 supply voltage protection . . . . . . . . . . . . . . . . 11 8.4 differential audio inputs . . . . . . . . . . . . . . . . . 11 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 10 thermal characteristics. . . . . . . . . . . . . . . . . . 12 11 static characteristics. . . . . . . . . . . . . . . . . . . . 13 12 dynamic characteristics . . . . . . . . . . . . . . . . . 14 12.1 switching characteristics . . . . . . . . . . . . . . . . 14 12.2 stereo se con?guration characteristics . . . . . 15 12.3 mono btl application characteristics . . . . . . . 16 13 application information. . . . . . . . . . . . . . . . . . 17 13.1 mono btl application . . . . . . . . . . . . . . . . . . . 17 13.2 pin mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 estimating the output power . . . . . . . . . . . . . . 17 13.3.1 single-ended (se) . . . . . . . . . . . . . . . . . . . . . 17 13.3.2 bridge-tied load (btl) . . . . . . . . . . . . . . . . . 18 13.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.5 heatsink requirements . . . . . . . . . . . . . . . . . . 19 13.6 pumping effects . . . . . . . . . . . . . . . . . . . . . . . 20 13.7 application schematic . . . . . . . . . . . . . . . . . . . 21 13.8 curves measured in reference design . . . . . . 23 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 15 soldering of smd packages . . . . . . . . . . . . . . 34 15.1 introduction to soldering . . . . . . . . . . . . . . . . . 34 15.2 wave and re?ow soldering . . . . . . . . . . . . . . . 34 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34 15.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 35 16 soldering of through-hole mount packages . 36 16.1 introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.2 soldering by dipping or by solder wave . . . . . 36 16.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 36 16.4 package related soldering information . . . . . . 37 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 37 18 legal information . . . . . . . . . . . . . . . . . . . . . . 38 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 38 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19 contact information . . . . . . . . . . . . . . . . . . . . 38 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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